TBCI Changelog

New in version 2.6.3

February 6th, 2012
  • This version has a few minor bugfixes and performance improvements.
  • The code has received minor adaptations to compile fine with icc-11.1 and gcc-4.5+.
  • Usage of HOT/COLD attributes has been implemented, but disabled by default (did not help in tests). cplx:power(double) has received a bugfix.
  • There are some cleanups and performance improvements in the SMP parallelization infrastructure.
  • Most notably, this release can do short busy-waiting before yielding a core, which results in less context switches and better SMP performance.

New in version 2.6.1 (September 8th, 2009)

  • The CPU detection code now handles intel hyperthreaded CPUs specially; it will by default only schedule a compute thread on one of the hyperthreads. This improves performance.
  • The packaging has been cleaned up and is now much more in line with openSUSE and Debian packaging conventions.

New in version 2.6.0 (September 8th, 2009)

  • This release features a few performance enhancements.
  • It will detect core2 and Nehalems correctly and optimize for them.
  • thread_control structures have been rearranged for reduced cacheline bouncing, especially for the thread-safe memory allocations via malloc_cache (binary incompatible with 2.5.x).
  • A few bugfixes have been made.