i815 linux tweak 0.1

i815 linux tweak project is i815-family chipset tweaker and optimizer for improve performance.
i815 linux tweak project is i815-family chipset tweaker and optimizer for improve performance. Remember that some settings can crash your system.

USE AT YOUR OWN RISK

Installation:

From root user tpye "./install.sh".
If success, module will compile and plased into modules directory.

Usage:

modprobe i815tweak

Without any parameters nothing changes. In /proc/i815info you can see actual chipset settings.

Or see "dmesg" for error info..

For list all module parameters check "modinfo i815tweak".

cas=[2,3]
CAS# Latency (CL)

ras2cas=[2,3]
SDRAM RAS# to CAS# Delay (SRCD)

ras=[2,3]
SDRAM RAS# Precharge (SRP)

refX=[0-7]
SDRAM Mode Select (SMS). These bits select the operational mode of the MCH DRAM interface. The special modes are intended for initialization at power up.

0 = DRAM in Self-Refresh Mode, Refresh Disabled
1 = Normal Operation, 100 MHz System memory – Refresh interval 15.6 uSec
133 MHz System memory – Refresh interval 11.7 uSec
2 = Normal Operation, 100 MHz System memory – Refresh interval 7.8
133 MHz System memory – Refresh interval 5.85 uSec
3 = Normal Operation, 100 MHz System memory – Refresh interval 1.28 uSec
133 MHz System memory – Refresh interval 0.96 uSec
4 = NOP Command Enable. In this mode all processor cycles to SDRAM result in a NOP Command on the SDRAM interface.
5 = All Banks Precharge Enable. In this mode all processor cycles to SDRAM result in an All Banks Precharge Command on the SDRAM interface.
6 = Mode Register Set Enable. In this mode all processor cycles to SDRAM result in a mode register set command on the SDRAM interface.
7 = CBR Enable. In this mode all processor cycles to SDRAM result in a CBR cycle on the SDRAM interface.

dct57=[0, 1]
DRAM Cycle Time (DCT). This bit controls the number of SCLKs for an access cycle.
0 = Tras = 7 SCLKs and Trc = 9 SCLKs.
1 = Tras = 5 SCLKs and Trc = 7 SCLKs (Default)

bnr=[0,1]
Block New Request Lookahead

agp=[0,1]
AGP4X Override

sba=[0,1]
Sideband Address Enable (SBA)
1 = Enable. The sideband addressing mechanism is enabled.
0 = Disable

fw=[0,1]
Fast Writes Enable (FW). This bit must always be programmed to 0. The chipset will behave
unpredictably if this bit is programmed with 1.

cpc=[0,1]
Command per cycle

sm=[0,1]
SM Always Bypass

hacqs=[0,1]
Host Aperture Cycle Queue Slot
0 = Default value. No dedicated queue
1 = A dedicated queue slot is reserved

clt=[0,1]
CPU Latency Timer
0 = Deferrable processor cycle will be Deferred immediately after receiving another ADS#
1 = Deferrable processor cycle will only be Deferred after in has been held in a “Snoop Stall” for 31
clocks and another ADS# has arrived (default).

dpcp=[0,1]
DRAM Page Closing Policy (DPCP)
0 = Precharge All during the service of any “Page Miss” access.
1 = Precharge All during the service of any “Page Miss” access.

magwe=[0,1]
Memory Arbiter Grant Window Enable (MAGWE).
0 = Disabled. Enforce fixed priority.
1 = 24 clocks limiting host, 24 clocks guaranteed to low priority graphics stream.

EXAMPLE:

modprobe i815tweak cas=2 ras2cas=2 ras=2 bnr=1 dct57=1

For more info about i815 chipset settings see Intel Document Reference Number 290688-001, 290693-001 and 290693-002

last updated on:
June 6th, 2007, 14:03 GMT
price:
FREE!
developed by:
Alexander Koryushkin
homepage:
sourceforge.net
license type:
GPL (GNU General Public License) 
category:
ROOT \ System \ System Administration

FREE!

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