UrJTAG 0.10

UrJTAG is a tool for communicating over JTAG with flash chips, CPUs, and many more.
UrJTAG is a tool for communicating over JTAG with flash chips, CPUs, and many more. It takes on the well proven openwince jtag tools code.

Future plans include conversion of the code base into a library that can be used with other applications. A flexible remote communication protocol that can be used over almost any type of serial link (including TCP/IP) is currently being defined.

JTAG (IEEE 1149.1) is a serial interface for testing devices with integrated circuits. The problem that the JTAG interface was designed to solve is checking if connections between ICs are OK. Therefore you can set and check in- and outputs of ICs. In order to save pins and logic a very simple serial design was invented.

� One pin serial input
� One pin serial output
� One pin clock
� One pin control

The control pin (together with clock) allows to switch device states. A state machine inside each chip can be controlled, e.g. to reset the device. This control machine also allows to have two internal shift registers in each device (although we only have on in- and one output-pin). The registers are called instruction register (IR) and data register (DR). The current UrJTAG tool allows you to set the IR and set and get the DR. It doesn't allow you to directly control the statemachine (yet).

Supported JTAG adapters/cables
� Arcom JTAG Cable
� Altera ByteBlaster/ByteBlaster II/ByteBlasterMV Parallel Port Download Cable
� Altera USB-Blaster and compatible http://www.ixo.de/info/usb_jtag
� Xilinx DLC5 JTAG Parallel Cable III
� ETC EA253 JTAG Cable
� ETC EI012 JTAG Cable
� Ka-Ro TRITON (PXA255/250) JTAG Cable
� Keith & Koep JTAG Cable
� Lattice Parallel Port JTAG Cable
� Mpcbdm JTAG Cable
� Macraigor Wiggler JTAG Cable
� Olimex FT2232-based ARM-USB-JTAG
� Other FT2232-based USB JTAG cables (experimental)
� Xilinx Platform USB Cable (experimental)

JTAG-aware parts (chips)

The data/ directory of the UrJTAG installation has some more, but at least the following are supported:
� Altera EP1C20F400
� Altera EPM7128AETC100
� Analog Devices Sharc-21065L
� Atmel ATmega128 (partial support)
� Broadcom BCM1250
� Broadcom BCM3310 (partial support)
� Broadcom BCM5421S
� Broadcom BCM4712 (partial support)
� DEC SA1100
� Hitachi HD64465
� Hitachi SH7727
� Hitachi SH7729
� IBM PowerPC 440GX
� Intel IXP425
� Intel SA1110
� Intel PXA250/PXA255/PXA260/PXA261/PXA262/PXA263
� Lattice LC4032V
� Lattice M4A3-64/32
� Lattice M4A3-256/192
� Motorola MPC8245
� Samsung S3C4510B
� Sharp LH7A400
� Toshiba TX4925/TX4926
� Xilinx XC2C256-TQ144
� Xilinx XCR3032XL-VQ44
� Xilinx XCR3128XL-CS144
� Xilinx XCR3128XL-VQ100
� Xilinx XCR3256XL-FT256

Flash chips

Note Not all chips are supported in every possible configuration, there may be untested combinations of chip type, bus width, �
� Intel 28FxxxJ3A (28F320J3A, 28F640J3A, 28F128J3A)
� Intel 28FxxxK3 (28F640K3, 28F128K3, 28F256K3)
� Intel 28FxxxK18 (28F640K18, 28F128K18, 28F256K18)
� AMD Am29LV64xD (Am29LV640D, Am29LV641D, Am29LV642D)
� AMD Am29xx040B (Am29F040B, Am29LV040B)

last updated on:
April 19th, 2009, 5:20 GMT
developed by:
Kolja Waschk
license type:
GPL (GNU General Public License) 
ROOT \ Science and Engineering \ Electronic Design Automation (EDA)


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What's New in version 0.9
  • The BSDL parser has been rewritten with added support for IEEE 1532 extensions.
  • Internally, many global variables were removed, which is a major improvement for everyone who wants to use UrJTAG as a library.
  • The low level communication with USB cables has been properly separated from that with parport cables into new "usbconn" and "parport" link drivers, making it easier to support new USB cables with their custom protocols natively.
  • Many annoyances and bugs have been fixed.
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