Signs 0.6.3

Signs is a tool for logic synthesis and gate level simulation.

  Add it to your Download Basket!

 Add it to your Watch List!


Rate it!
send us
an update
BSD License 
3.3/5 21
Signs Team
ROOT \ Science and Engineering \ Electronic Design Automation (EDA)
3 Signs Screenshots:
Signs is a tool for logic synthesis and gate level simulation. Signs's project main features include synthesis of RTL-style VHDL circuit descriptions and a dynamic graphical netlist viewer.

Supported formats include VHDL, ISCAS, and limited support for BLIF, Verilog, and EDIF netlists. Various true value and fault simulators and a combinational ATPG are included for circuit testing.

Aside from GUI mode, Signs has a pure command line mode and is fully scriptable in JavaScript and Ruby.

Here are some key features of "Signs":

Written in Java, therefore platform-independent
Aims to be VHDL93 compliant, at the moment a VHDL Subset is supported
(Limited) support for non-synthesizable VHDL code, useful for testbenches
Synthesis of RTL-style sequential VHDL process descriptions according to IEEE Std 1076.6
Dynamic graphical netlist viewer supporting annotations (signal/gate names, signal values provided by simulators, faults)
VHDL netlist output to file
Input and output of netlists in ISCAS benchmark format
Gate level true value simulators: event-based (any circuit), bit-parallel (combinational circuits only)
Fault simulators: PPSFP, simple single faultsim
Input and output of pattern lists in WGL format
ATPG for combinational circuits: Implication-Graph based, PODEM
Limited support for Verilog and EDIF netlists
Fully scriptable in Rhino: JavaScript for Java and JRuby
Pure command-line mode available besides GUI mode
Integrated environment including source code and netlist structure tree views, build system, compilers and editors with syntax highlighting

What's New in This Release:

While the release focus is clearly on bugfixes, there are also some feature improvements, such as enhanced test bench support and improved netlist and simulator views.
The VHDL compiler has support for subprograms now and elaboration of big designs is much faster because of improved context handling.
Internally, the intermediate representation layer was cleaned up, so intermediate objects form a proper tree now.

Last updated on January 11th, 2007

#gate level simulation #logic synthesis #Signs #gate #level #simulation

Add your review!