Dolphin Smash is a mixed-signal, multi-language simulator for IC or PCB designs. Dolphin Smash extends its capabilities for mixed signal code-coverage and sensitivity-analysis up to detecting flaws in Virtual Testbenches and to identifying circuit weaknesses for the DfM conscious designer.
Improvement on the block-busting GUI features facilitate further the adjustments of speed versus accuracy, as well as tracing, now augmented for a hierarchical view applicable to mixed signal design.
With analysis of sensitivity to dispersion, SMASH provides a fast and accurate solution for the problems of design for yield, manufacturability and robust design of nano-electronic analog circuits. Compared to Monte Carlo analysis, the sensitivity to dispersion is thousands of times faster. Furthermore, the sensitivity to dispersion analysis provides the contribution of each component to the total dispersion, thus design debugging becomes trivial.
As SCROOGE enables power consumption analysis before Place & Route, the SPEF back-annotation now provides it with parasitic capacitance back-annotation for an accurate power consumption analysis after Place & Route. Parasitic capacitances are taken into account to back-annotate the Liberty wire load model. This allows to consider the exact routing capacitance both for cell interconnection wires and for clock trees, which represent an important part of the consumed power.
For increased interoperability, simulation results can now be exported into standard VCD (Verilog Change Dump) format for logic or CSDF (Common Simulation Data Format) for reuse in all compatible EDA solutions. Of course, SMASH can also import and display VCD or CSDF results as well as.
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Here are some key features of "Dolphin Smash":
· Code coverage for HDL-AMS
· DC & small-signal dispersion sensitivity analysis
· Power consumption estimation after Place & Route with SPEF back-annotation
· Enhanced GUI with tree view selection of traces and interactive logging panes
· BSIM4v5 update including a well proximity effect model
· CSDF and VCD output formats for exporting of analog and logic simulation results
· VDA automotive libraries bundled
What's New in This Release: [ read full changelog ]
· This version implements major improvements among which domain coloring for a first approximation of the pole/zero locations, a .PZ directive for pole/zero analysis, support of .wav files as ouput of logic designs, and CCS segmentation extraction processing functions.
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