Alliance CAD System

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5.0.20070718 GPL (GNU General Public License)    
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Alliance CAD System are EDA tools for VLSI design.

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Alliance is a complete set of free CAD tools and portable libraries for VLSI design. Alliance CAD System includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools.

A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).

Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.

Alliance provides CAD tools covering most of all the digital design flow:

VHDL Compilation and Simulation
Model checking and formal proof
RTL and Logic synthesis
Data-Path compilation
Macro-cells generation
Place and route
Layout edition
Netlist extraction and verification
Design rules checking
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Last updated on July 30th, 2007

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