DREAM Tool is a generic framework that aims at providing a common semantic domain which can express several (real-time, power consumption, resource) constraints.
The semantic domain has an executable C++ model which has been semantically anchored to the hybrid automata formalism. Although the model of computation corresponds to hybrid automata, so far we have been successful in analyzing the models by conservative approximation using timed automata on moderate size systems.
To deal with large-scale examples the user has the ability to use the simulation/testing interface on the executable C++ model before implementing the system. We plan to extend the genetic algorithms to solve a large number of problems.
DREAM is a simulation and verification framework which provides a formal model and analysis of your system in less than a day. Systems in DREAM are specified using XML in a straightforward way. I hope you find it useful.
Real-time middleware provides dependable and efficient platforms supporting key functional and quality of service (QoS) needs of distributed real-time embedded (DRE) systems.
Key challenges in DRE system developments include safe composition of system components and mapping the functional specifications onto the target platform. Model-based technologies help address these issues by enabling design-time analysis and providing the means for the rapid evaluation of design alternatives with respect to end-to-end QoS properties, predictability and performance measures before committing to a specific platform.
The Distributed Real-time Embedded Analysis Method DREAM is an open-source tool and method for optimizing multiple quality of service (QoS) properties of distributed real-time embedded (DRE) systems. The project focuses on the practical application of formal analysis methods to real-time middleware to automate the verification, development, configuration, and integration of middleware-based DRE systems.
What's New in This Release:
· This version implemented several optimizations for improved model checking performance, resulting in impressive performance gains of at least 2-3 times.
· There are no known memory leaks present in the current release.
· Balanced AVL trees are now used, resulting in exponential speedups in several steps of the model checking method.
· XML Schema validation was implemented.
· Verification time reporting was upgraded to include data on the simulation speeds.
· Random simulation-based testing now provides an execution trace when a deadline is missed.