A graphical editor for finite state machines.
Finite state machines are a model to describe complex objects or systems in terms of the states they may be in. In practice they can used to design integrated circuits or to create regular expressions, scanners or other program code.
- Drawing, editing and printing of diagrams
- Binary, ASCII and "free text" condition codes
- Multiple windows
- Integrity check
- Interactive simulation
- AHDL/VHDL/Verilog HDL/KISS export
- State table export in Latex, HTML and plain text format
- Ragel file export (used for C/C++, Java or Ruby code generation)
In a hurry? Add it to your Download Basket!
What's New in version 0.52
- We just released version 0.52 which fixes some bugs and introduces some new features, e.g. VHDL testbench export, vvvv Automata export and SCXML export. Moreover, the user manual has been overhauled.